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Silicon Labs /SiM3_NRND /SIM3L167_C /LCD_0 /CLKCONTROL

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Interpret as CLKCONTROL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKDIV0 (DIVIDE_BY_1)RTCCLKDIV

RTCCLKDIV=DIVIDE_BY_1

Description

Clock Control

Fields

CLKDIV

Clock Divider.
RTCCLKDIV

RTC Input Clock Divider.

0 (DIVIDE_BY_1): undefined

1 (DIVIDE_BY_2): undefined

2 (DIVIDE_BY_4): undefined

3 (DIVIDE_BY_8): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data